The invention relates to the general field of semiconductor devices, and in particular to a Field Effect Transistor FET having a drain with a lightly doped region acting as a ballast resistor.
Electrostatic discharge (ESD) pulses can damage or destroy integrated circuits. Protection becomes more difficult as process structures are shrunk. For submicron processes, ESD protection is a major reliability concern, and adequate ESD protection is not easily achieved.
For example, when a device receives an ESD pulse having a magnitude on the order of a thousand volts, a large voltage gradient is created between the contact and the channel. This gradient can accelerate charge carriers, ionize conduction paths, and inject electrons into the gate oxide above the channel region. This "hot carrier" effect can cause device failure through permanent damage. Even if the device does not fail, hot electrons can change the device characteristics. In addition, the conduction paths can heat up until the silicon melting point is reached and the device junctions are permanently destroyed.